FPGA Demo Lab | Matt Hales

FPGA project

Project workspace

Choose a project to explore its workspace. The FPGA image is loaded when an approved job runs.

Checking hardwareSysBase verification pilot

Queue unavailableUp to 8 × 8150 MHz image

Matrix Workspace

Configure a square matrix multiplication and inspect how the work is tiled.

C = A × B

Output tile map

Architecture view · not live telemetry

Hardware tile4 × 4

Output tiles2 × 2 = 4

Shared-dimension passes2 per output tile

Selected output tile

C[1, 1]

Rows 1–4
Columns 1–4

Accumulate 2 tile products along the shared dimension to build this section of C.

CPU vs FPGA

Measured timings from a run of the selected profile.

CPU reference—

FPGA kernel—

Runner total—

Host → device—

Device → host—

Verification—

Performance comparison

Kernel speedup—

Runner-total speedup—

Speedup is CPU reference time divided by the corresponding FPGA time. Pilot kernel timing measures host launch and wait for completion. Runner total includes device transfers, kernel execution and status readback; CPU reference/verification, process setup, image loading and queue waiting are excluded. A result below 1× means the FPGA took longer for that measurement.

Submit a job when the hardware is available. No benchmark data is shown until a run completes.

Why larger matrices?

A logical matrix can be larger than the compute array. Tiling reuses the hardware across portions of the input, then combines the partial products.

This validated pilot accepts dimensions up to 8. Measured performance depends on the workload, transfer costs, and CPU baseline.